The present technique relates to an apparatus and method for operating a virtually indexed, physically tagged cache.
When using such a cache, a virtual address is used to identify a number of entries within the cache (those number of entries typically being referred to as a set within an N-way set associative cache), and then the corresponding physical address is used to determine if a hit or a miss has occurred, by comparing the relevant portion of the physical address with physical address tag values stored within the identified entries of the cache. Such an approach allows the cache lookup operation to begin in parallel with address translation, with the physical address only being needed for hit/miss determination once the tag array lookup has been performed.
However, a potential problem that can arise occurs as a result of aliasing. In particular, aliasing occurs when different virtual addresses are mapped to the same physical address. Whilst this may be allowed behaviour and may not have a negative impact per se, there are situations where it can cause complications in respect of a virtually indexed, physically tagged cache. In particular, it is possible that the different virtual addresses for the same physical address may identify different sets within the cache. This can result in duplication within the cache, reducing the effective size of the cache, and also may give rise to coherency issues due to the fact that it is necessary for the multiple different entries in the cache to have the same value.
It would be desirable to reduce the potential adverse effects of aliasing when employing a virtually indexed, physically tagged cache.